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ISL97671
1
S
7
Slave Address
1
W
1
A
8
Command Code
1
A
8
Data byte
1
A
1
P
Master to Slave
Slave to Master
FIGURE 27. WRITE BYTE PROTOCOL
1
S
7
Slave Address
1
W
1
A
8
Command Code
1
A
1
S
8
Slave Address
1
R
1
A
8
Data Byte
1
A
1
P
Master to Slave
Slave to Master
FIGURE 28. READ BYTE PROTOCOL
SMBus/I 2 C Communications
The ISL97671 can be controlled by SMBus/I 2 C for PWM or DC
dimming. The LEDs driving is defaulted to off and the users will need
the SMBus/I 2 C interface to enable the driving and controlling of
various parameters that will be described in this section. Please
note that the ISL97671 can also be controlled by an external PWM
signal for PWM dimming without any SMBus/I 2 C interface. To do so,
the users need to pull the SMBCLK and SMBDAT pins to low or
ground the pins permanently if SMBus/I 2 C control is not used. The
switching frequency is fixed at 600kHz if SMBus/I 2 C is not used.
Write Byte
The Write Byte protocol is only three bytes long. The first byte starts with
the slave address followed by the “command code,” which translates to
the “register index” being written. The third byte contains the data byte
that must be written into the register selected by the “command code”.
A shaded label is used on cycles during which the slaved backlight
controller “owns” or “drives” the Data line. All other cycles are driven by
the “host master.”
Figure 29, the high nibble of the Slave Address byte is 0x5 or 0101b
to denote the “backlight controller class.” Bit 3 in the lower nibble of
the Slave Address byte is 1. Bit 0 is always the R/W bit, as specified
by the SMBus/I 2 C protocol. Note: In this document, the device
address will always be expressed as a full 8-bit address instead of
the shorter 7-bit address typically used in other backlight controller
specifications to avoid confusion. Therefore, if the device is in the
write mode where bit 0 is 0, the slave address byte is 0x58 or
01011000b. If the device is in the read mode where bit 0 is 1, the
slave address byte is 0x59 or 01011001b.
The backlight controller may sense the state of the pins at POR or
during normal operation - the pins will not change state while the
device is in operation.
SMBus/I 2 C Register Definitions
The backlight controller registers are Byte wide and accessible via the
SMBus/I 2 C Read/Write Byte protocols. Their bit assignments are
provided in the following sections with reserved bits containing a
default value of “0”.
Read Byte
MSB
LSB
As shown in Figure 28, the four byte long Read Byte protocol starts
out with the slave address followed by the “command code” which
0
1
0
1
1
0
0
R/ W
translates to the “register index.” Subsequently, the bus direction
turns around with the re-broadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains the data
being returned by the backlight controller. That byte value in the
data byte reflects the value of the register being queried at the
“command code” index. Note the bus directions, which are
highlighted by the shaded label that is used on cycles during which
DEVICE
IDENTIFIER
DEVICE
ADDRESS
the slaved backlight controller “owns” or “drives” the Data line. All
other cycles are driven by the “host master.”
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W bit, but
these 8 bits are usually called Slave Address bytes. As shown in
17
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION
FN7631.3
August 14, 2012
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